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Embedded Test Improves Yield and Time to Market,By Paul Price
At-speed testing eliminates tester guardband and improves chip quality

System-on-chip (SoC) devices containing processors, memories, IP cores, glue logic, mixed-signal, high pin counts, and high clock frequencies are challenging today’s conventional test technologies. Automatic test pattern generation (ATPG) and functional tests applied through external Automatic Test Equipment (ATE) are increasingly difficult, with pin counts exceeding 1000 and clock frequencies approaching 1 GHz. At the same time, engineers increasingly accept the fact that yield is a critical factor in successful chip design.

Prior to SoCs, function specific testers were used to separately test logic, memories and mixed signal devices. With multiple functions now integrated onto a single device, multi-function high cost ATE are now required. With tester costs already in the millions of dollars, these solutions are quickly becoming cost prohibitive. Furthermore, it is well known that some problems are fundamentally impossible to solve using external testers.

What is needed is a total design for testability solution that can provide at-speed test of all embedded blocks including logic, memory, and mixed-signal using associated best case fault models. The solution should be able to reduce test time, allow companies to better utilize their existing investment in test infrastructure, provide higher fault coverage and better diagnostics, while reducing time to market.

So now more than ever, as the industry moves to 90-nanometer process geometries and beyond, embedded test techniques can improve yields and decrease time to market. (see Figure 1)

Figure 1: SoCs that integrate processor, memory, logic and mixed-signal are challenging conventional IC test methodologies with increasing complexity, high clock speeds and high pin counts.

Articulating embedded test

The basic concept of embedded test is that the designer embeds multiple “micro testers�?-different types such as logic, memory, and mixed-signal testers-inside the die to test functional structures rather than using external access and patterns. Typically, the industry standard IEEE 1149.1 5-pin Test Access Port (TAP) is used as a means to interface to the various embedded testers, simplifying the tester interface.

Embedded memory testers utilize internal pattern generation to apply and compare deterministic sequences such as March algorithms to test a memory. These testers will typically identify 100 percent of the defects targeted by a particular algorithm. In the case of random logic test, a pseudo-random pattern generator applies test stimulus and results are compressed at-speed and compared to a signature predicted through simulation.

When compared to traditional ATPG approaches, test coverage of defects can prove significantly more effective due to the high number of patterns applied to the circuit. The typical cost of embedded test is less than 5 percent of the die size.

Once embedded test capabilities are on the die, debug software can utilize the embedded test structures to validate structural integrity and isolate failures. Together, debug software and embedded test provide a structured approach to achieving higher yields, higher quality, faster silicon debug times and first-time silicon success.

Embedded test combines external ATE functionality with conventional Design-for-Test (DFT) methodologies to automate test, diagnosis, and debug processes. Embedded test seamlessly integrates multiple disciplines of scan, built-in self test (BIST), results collection, and precision high-speed timing. The technology provides benefits throughout the life of the product including high quality manufacturing testing, fast first silicon debug, more effective board and system test and remote field debug and diagnosis.

Aims and intentions

The aim of embedded test is to incorporate ATE features on the chip including test pattern generation, results compression and timing generation to match process performance. Embedded test is both a collection of on-chip testers, referred to as “embedded test controllers,�? and an access and control infrastructure for effectively leveraging these testers.

Embedded test controllers are typically accessed from a single IEEE standard TAP. The TAP includes a controller, which acts as a test manager, initializing and running all embedded test controllers based on instruction register operation codes. The TAP also controls the boundary scan register, which can be used for I/O test or board-level test and is the most convenient way to isolate the logic under test from external influences that might affect expected test signatures.

Boundary scan is a structured DFT technique developed in the late 1980s by the Joint Test Action Group (JTAG) and standardized in 1990 by the IEEE as a fundamental component of the 1149.1 standard. When applied to the input and output pins of an SoC, boundary scan enhances accessibility and testability. With boundary scan, each input/output (I/O) bonding pad has an associated shift-register stage (contained in a boundary scan cell). Shown in our example SoC, the boundary scan cells are inserted between the I/O pads and the core logic. (see Figure 2)

Figure 2: Embedded Test combines external ATE capabilities with conventional DFT methodologies inside the chip to simplify and automate test, diagnosis and debug processes from outside the chip.

In addition, embedded test can be implemented as a hierarchical DFT strategy that reduces, if not eliminates, the need for external test. Although the embedded test approach requires more silicon area, the savings realized through automation of the testing process, higher quality of testing, and reuse at all the levels of the design hierarchy make this DFT method very attractive. Each embedded test controller contains an asynchronous interface to setup the controller through the TAP at a slow test clock rate while keeping the clock source to the controller at full system rate. A finite state machine manages the flow of execution for all of the embedded test controllers.

In the case of embedded memory test, the embedded test controller controls the application and comparison of the deterministic patterns. For embedded logic test, the associated embedded test controller controls when to start generating random patterns, when to start accumulating capture results into a Signature Register, and when to compare the reference signature. A waveform generator supplies all scan and clock-enable signals as well as all clocks required to control the scan chains. A pseudo-random pattern generator supplies output patterns to load the scan chains. A sequencer controls the internal scan chains and boundary scan chains. Returning captured data from the scan chains is compressed into a predictable signature and compared against a hardwired reference signature.

Integrating embedded test

Applying embedded test to an example SoC, we first add embedded test controllers to the lower-level sub-blocks of the design. This includes embedded test controllers to test embedded memories, repairable memories, random logic, PLLs, and so forth. In parallel, we can add the TAP and boundary scan around the entire chip enabling control and observation of every pin. (see Figure 3)

Figure 3: Adding embedded memory test and boundary scan (a), embedded logic test to the lower-level blocks (b), and the top-level embedded logic test and test connectivity. (c)

Much of the embedded test integration can be done at the RTL level, simplifying the insertion, verification, and timing closure for these structures. After the sub-block implementation is completed, the design can be synthesized and made scan-ready to allow for embedded logic test implementation.

In order to add embedded logic test controllers to each sub-block or the top level, the design must conform to a specific set of design rules. In scan mode, the logic must be fully synchronous and scan-compliant. Synchronous design rules require the logic block to be composed of combinational logic and D-type flip-flops. All flip-flops are required to be clocked from a primary input pin. The clocks can be gated by the combinational logic, useful in low power designs.

Multiple clock domains are also allowed. The embedded logic test controller handles multiple clock domains by applying half- and quarter-clock frequencies to the additional domains. To be scannable, standard flip-flops must be replaced with multiplexed scan flip-flops, which are automatically connected into scan chains. Set-reset latches and transparent latches are not fully testable and should be replaced, whenever possible, by D-type flip-flops. Three-state gates are allowed only when designed to allow a single bus driving at one time.

Conformance to specific design rules is verified through common rule checking engines. Once a block is scan-ready and determined to conform to the above rules, an embedded logic test controller can be generated that maps directly to the block-under-test based on the frequency of operation, the number of scan chains, and the fault-coverage targets. There are typically automation tools to connect or integrate the controller to the block.

Tool implementation

Once the hardware implementation is complete, tools can be used to fully analyze fault coverage and determine the signatures for the design. As soon as the block-level implementation is complete and verified, these can be handed off to the physical design team to complete the layout process of the block, knowing that no top-level test implementation will affect the block-level layout. (see Figure 4)

Figure 4: Glue logic is controlled and observed when the embedded logic test controller applies scan data, controls, and at-speed clocks. In scan mode, the logic must be fully synchronous and scan-compliant. Synchronous design rules require the logic block to be composed of combinational logic and scannable D-type flip-flops.

Finally, at the top-level of the SOC, all the lower-level controllers are connected to the TAP to allow simple programmability and control. Depending on the implementation, a top-level embedded logic test controller may also be added to test any glue logic sitting at the top level, as well as test the interconnect between the sub-blocks. All verification tests generated at the block level can be re-targeted and re-run from the top level of the device.

After completion of the top-level integration and verification, the top-level physical implementation can be completed. Once the physical implementation is complete at the block or top level, these should be re-verified from a test perspective just like the function of the blocks are re-verified from a functional perspective.

After the TAP controller initializes and initiates the embedded logic test controller, the Pseudo Random Pattern Generator shifts a new pattern into the scan inputs of all scan chains associated with the logic block. On completion of the scan loading, ScanEnable controls are lowered for a single, at-speed, clock cycle to capture the functional logic block response. This capture cycle operation is identical to the normal functional operation of the logic block for a particular setup condition. Since the capture is performed at-speed, any slow-to-rise or slow-to-fall transitions (delay defects) will be detected.

Following the capture cycle, ScanEnable controls are raised and the capture data is shifted out while, simultaneously, a new pseudo-random pattern is shifted in. The capture data streams are compressed using a cyclic-redundancy checker (CRC) to produce a new signature, which is accumulated in the Signature Register. The shift/capture cycle is repeated for a pre-determined pattern count. On completion, the final signature is shifted off-chip and compared with the expected final result to produce a pass/fail decision. (see Figure 5)

Figure 5: Embedded logic test controller applies numerous pseudo-random patterns on-chip at system clock rates and captures results, at-speed, providing high defect coverage for slow-to-rise and slow-to-fall faults.

Time-to-market benefits

As stated earlier, embedded test can provide many benefits throughout the lifecycle of a device. The idea that embedded test can positively impact the areas of yield, quality, and cost is now widely accepted. An embedded test strategy can also have a large impact on time to market through extremely powerful device debug and root cause failure analysis.

Higher product yield is attained by the elimination of guardbanding and the reduction of pin-contact requirements. As SoC clock frequencies move beyond the tester’s ability to measure speed performance using external vectors, test engineers add a guardband to guarantee meeting the speed specification. Yield loss can result by binning faster devices in slower bins, which effectively eliminates many good die. When embedded test is used, the die is tested at-speed with the at-speed stimulus being generated within the device. No guardband is required, providing the highest possible yield.

Further yield savings can be achieved by minimizing the number of contacts required to test a device, especially at wafer probe. This results in fewer discarded good parts due to bad contacts. The cost savings from these yield factors can have significant impact on product profitability.

Higher quality can also be obtained through a combination of at-speed testing and the inherent n-detect or multi-detect enabled by embedded test. While the manufacturing engineer may be confident of high stuck-at-fault coverage for externally applied vectors (slow-speed ATPG patterns), other defect types such as transition faults (slow-to-rise and slow-to-fall faults), bridging faults, coupling faults, and so forth, may never be detected-reducing the product quality. Embedded test not only detects these defects, but also provides a means by which to provide root-cause diagnosis.

Controlling manufacturing costs

Embedded test can help better manage manufacturing costs by shortening test times and eliminating the need to migrate to faster testers with higher pin counts. By running the entire chip at-speed and using test points to achieve coverage with fewer patterns, faster test times are achieved using minimum pattern counts.

In one example, embedded test achieved a test time of 2 seconds compared to 8 seconds using conventional testing for a 10 million gate SoC with 512KB SRAM running a 250 MHz core clock. The pattern count for such a test is on the order of 30K vectors, as opposed to the millions of vectors (and potentially multiple tester loads) that would have been required using conventional test techniques.

As mentioned earlier, embedded test also reduces the dependence on expensive ATE. Increasing tester costs are attributed to faster pin electronics and the need to store more memory for larger patterns required for more complex chips. Finally, because the tester is on-chip and there is a reduced pin-count interface, very little pattern memory is required to run embedded tests. At the least, embedded test can help extend the life of any current tester investment.

Finally, integrated design and turnkey debug reduce time to market significantly. Because of the at-speed nature of the tests and the fact that the tester is now inside the silicon, embedded test provides a robust, repeatable solution to device debug and defect isolation. Bring-up time for first silicon can be reduced to hours instead of days or weeks. Design debug can be in days instead of months.

Debug and diagnosis at the chip level is enabled with full control and observation of the embedded test controller’s internal registers (pattern length seed of pattern generator, signature register, etc), full observation of internal scan chains, and full control of the clock sources (system clock pin, PLL output, and TAP clock).

EDA flows and methodologies

Embedded test requires cooperation between design, test and manufacturing groups throughout the entire development process. No longer can testing be an after-thought. It needs to be incorporated as a function of the device. The design team must decide on the test strategy from the beginning of the project. In the first step of an embedded test design flow, the design engineer must run the rules checkers to confirm that the chip meets requirements for synchronous design. Next, the RTL IP design objects for the embedded test controllers as well as for the boundary scan and TAP must be integrated into the design.

All of this requires a good understanding of the specific EDA flow that is used by a design team as well as the automation and integration capability provided by today’s embedded test tool providers. With appropriate foresight and planning, a well-integrated flow that is consistent with the team’s goals of fast turn around time, quality, and manufacturability can be achieved.

From a manufacturing perspective, embedded test solutions today allow test engineers and production manufacturing teams to utilize all of the infrastructure that is currently in place for pattern translation and bring-up on a manufacturing test floor. What is new in this space are the solutions that allow more complete automation of the entire test development, bring-up, and debug process to allow quicker root-cause resolution of problems related to design, manufacturing, or the test setup itself.

As the benefits of higher yield, higher quality, and time to market become apparent, the embedded test design flow will be no longer be thought of as a back-end problem. Instead, embedded test will be embraced as an accepted component of a standard design process, and will be taken into consideration much earlier in the design process. Everyone will benefit as a result- the designer, the manufacturer, and the end-user of the more robust, more defect-free products.

Paul Price is senior director of applications engineering at LogicVision Inc. (San Jose, CA). Price has over 15 years of experience in the semiconductor industry. He received his BSEE from Rose-Hulman Institute of Technology and his Masters from Cornell University.



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